1. Field of Invention
The present invention generally relates to a semiconductor package, and more particularly, to a semiconductor package which has a novel shape capable of accomplishing a light, thin, compact and miniaturized structure.
2. Description of the Related Art
Recently, as the development of the electronic industry is rapidly progressed and light weight, miniaturization and multi-functionality of electronic products are required, an incorporated type semiconductor package in which a driving chip and a memory chip are constructed in one module has been developed. As a kind of the incorporated type semiconductor package, a structure in which a driving chip and a memory chip are fabricated as separate packages and the packages are vertically stacked or horizontally mounted on a mother board has been suggested.
FIGS. 1 and 2 are cross-sectional views illustrating conventional semiconductor packages. FIG. 1 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are vertically stacked, and FIG. 2 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are horizontally mounted on a mother board 30.
However, in the case where the driving package 10 and the memory package 20 are vertically stacked, problems are caused in that a signal transfer path between the driving package 10 and the memory package 20 is lengthened and complicated, and, in the case where the driving package 10 and the memory package 20 are horizontally mounted on the mother board 30, problems are caused in that the area of the mother board 30 occupied by the driving package 10 and the memory package 20 increases and it is difficult to accomplish miniaturization.
Additionally, in the memory package 20, in order to realize a product with a memory capacity at least two times larger than a memory capacity obtainable through a semiconductor integration process, at least two memory chips 2 are stacked, and the stacked memory chips 2 and a substrate 3 are connected using wires W. After forming the wires W, in order to protect the memory package 20, a molding part 5 is formed to seal the upper surface of the substrate 3 including the stacked memory chips 2.
While the wires W should have loops to define spaces for preventing short-circuiting with the peripheries of the memory chips 2, the size of the memory package 20 increases due to the presence of the wire loops and miniaturization is difficult to accomplish. Also, difficulties care caused in that a spacer 4 should be additionally formed between the stacked memory chips 2 to secure the height of the wire loops.
Also, as the number of stacked memory chips 2 increases, the height of the wire loops which are formed on the upper surface of the memory chip increases, and thus, limitations exist in increasing the number of memory chips 2 to be stacked. Moreover, as the number of stacked memory chips 2 increases, the length of wires W increases, and thus, problems are likely to be frequently caused due to wire sweeping, wire damage and short-circuiting between the peripheries of the memory chips 2 and the wires W during a process for forming the molding part 5. In addition, since the wires W should be formed using gold which is expensive, the package fabrication cost is increased.
In the case of grinding the memory chips 2 as thin as possible, although the number of memory chips 2 to be stacked may be increased, a fail such as a warpage and a crack is likely to occur.